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Hybrid dilated banyan networks with bypasses
http://hdl.handle.net/2241/6368
http://hdl.handle.net/2241/63684100c00b-1002-442c-80ea-bae941d6d0db
Item type | Thesis or Dissertation(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2007-07-25 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Hybrid dilated banyan networks with bypasses | |||||
言語 | ||||||
言語 | jpn | |||||
資源タイプ | ||||||
資源 | http://purl.org/coar/resource_type/c_db06 | |||||
タイプ | doctoral thesis | |||||
アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
著者 |
Komain,Pibulyarojana
× Komain,Pibulyarojana |
|||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In order to provide high speed multimedia network communication services such as voice, data and real-time video transmissions, the demand for B-ISDN (Broadband Integrated Services Digital Network) has been recently increased. A basis for packet transmission in B-ISDN, Asynchronous Transfer Mode (ATM)[1] has been introduced. ATM is a high-speed connection-oriented packet-switching technique with minimal functionality in the network which differs from the conventional packets switching in many aspects. High-level protocol functions such as error control are performed on an end-to-end basis, not such as link-by-link basis in ATM. In ATM, the multiplexing of transmission capacity into short fixed length transmission slots called cells has been adopted as a flexible and efficient transmission standard. The ATM cell consist of a 48 bytes information payload and a 5 bytes header[1]. The cell requires a mere total of 3 μs for transmission on a 155.12 Mb/s ATM link. Each cell header conrains an n-bit binary address of the requested output port. These cells are entered and distributed to their destinations, respevtively, by an ATM switch[2]-[5]. An ATM switch of size N can be regarded as a box with N input ports and N output ports. It routes cells arriving at its input ports in a time-slotted fashion to their desired output ports (destined by their headers). Since all input lines are synchronized and the minimum slot size is equal to the transmission time of a single cell, input and output lines are assumed to operate at the same speed. ・・・ | |||||
言語 | en | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | Bibliography: p. 66-68 | |||||
言語 | en | |||||
書誌情報 |
発行日 2000 |
|||||
取得学位 | ||||||
学位名 | 博士(工学) | |||||
取得学位 | ||||||
学位名 | Doctor of Philosophy in Engineering | |||||
学位授与大学 | ||||||
学位授与機関識別子Scheme | kakenhi | |||||
学位授与機関識別子 | 12102 | |||||
言語 | ja | |||||
学位授与機関名 | 筑波大学 | |||||
言語 | en | |||||
学位授与機関名 | University of Tsukuba | |||||
学位授与年度 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 1999 | |||||
学位授与年月日 | ||||||
学位授与年月日 | 2000-03-24 | |||||
報告番号 | ||||||
学位授与番号 | 甲第2370号 |