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Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure
http://hdl.handle.net/2241/114818
http://hdl.handle.net/2241/1148180bbf271a-74e2-40e0-8a36-1f74d3cbc7fa
名前 / ファイル | ライセンス | アクション |
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SSE_65-66.pdf (1.4 MB)
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Item type | Journal Article(1) | |||||
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公開日 | 2012-01-16 | |||||
タイトル | ||||||
タイトル | Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源 | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
著者 |
Sato, Soshi
× Sato, Soshi× Kakushima, Kuniyuki× Ahmet, Parhat× Ohmori, Kenji× Natori, Kenji× Yamada, Keisaku× Iwai, Hiroshi |
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著者別名 |
大毛利, 健治
× 大毛利, 健治× 山田, 啓作 |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. 〈1 0 0〉-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (1 0 0)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100° at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded. Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100° is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs. | |||||
書誌情報 |
Solid-state electronics 巻 65–66, p. 2-8, 発行日 2011-11 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 0038-1101 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA0084461X | |||||
DOI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1016/j.sse.2011.06.011 | |||||
権利 | ||||||
権利情報 | © 2011 Elsevier Ltd. “NOTICE: this is the author's version of a work that was accepted for publication in Solid-state electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in PUBLICATION, Vol.65–66, 2011, DOI;10.1016/j.sse.2011.06.011” |
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著者版フラグ | ||||||
値 | author | |||||
出版者 | ||||||
出版者 | Elsevier | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2241/114818 | |||||
識別子タイプ | HDL |