{"created":"2021-03-01T07:04:01.967039+00:00","id":25871,"links":{},"metadata":{"_buckets":{"deposit":"a6372db3-d1bf-4f5a-ba64-55e3d0787d10"},"_deposit":{"id":"25871","owners":[],"pid":{"revision_id":0,"type":"depid","value":"25871"},"status":"published"},"_oai":{"id":"oai:tsukuba.repo.nii.ac.jp:00025871","sets":["117:1710","117:1711","3:62:5601:1661"]},"item_5_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-11","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"8","bibliographicPageStart":"2","bibliographicVolumeNumber":"65–66","bibliographic_titles":[{"bibliographic_title":"Solid-state electronics"}]}]},"item_5_creator_3":{"attribute_name":"著者別名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大毛利, 健治"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山田, 啓作"}],"nameIdentifiers":[{}]}]},"item_5_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. 〈1 0 0〉-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (1 0 0)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100° at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded. Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100° is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.","subitem_description_type":"Abstract"}]},"item_5_identifier_34":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_identifier_type":"HDL","subitem_identifier_uri":"http://hdl.handle.net/2241/114818"}]},"item_5_publisher_27":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Elsevier"}]},"item_5_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1016/j.sse.2011.06.011","subitem_relation_type_select":"DOI"}}]},"item_5_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"© 2011 Elsevier Ltd.\n“NOTICE: this is the author's version of a work that was accepted for publication in Solid-state electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in PUBLICATION, Vol.65–66, 2011, DOI;10.1016/j.sse.2011.06.011”"}]},"item_5_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"author"}]},"item_5_source_id_7":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0038-1101","subitem_source_identifier_type":"ISSN"}]},"item_5_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA0084461X","subitem_source_identifier_type":"NCID"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Sato, Soshi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kakushima, Kuniyuki"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ahmet, Parhat"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ohmori, Kenji"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Natori, Kenji"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yamada, Keisaku"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Iwai, Hiroshi"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2013-12-25"}],"displaytype":"detail","filename":"SSE_65-66.pdf","filesize":[{"value":"1.4 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"SSE_65-66.pdf","url":"https://tsukuba.repo.nii.ac.jp/record/25871/files/SSE_65-66.pdf"},"version_id":"c66937a3-4f59-4412-b556-0215ec1be0d7"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure"}]},"item_type_id":"5","owner":"1","path":["1710","1711","1661"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-01-16"},"publish_date":"2012-01-16","publish_status":"0","recid":"25871","relation_version_is_last":true,"title":["Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-04-27T08:53:04.717259+00:00"}