{"created":"2021-03-01T07:29:11.934059+00:00","id":49039,"links":{},"metadata":{"_buckets":{"deposit":"107ff8c7-819a-4e92-b612-e6ab50c99a02"},"_deposit":{"id":"49039","owners":[],"pid":{"revision_id":0,"type":"depid","value":"49039"},"status":"published"},"_oai":{"id":"oai:tsukuba.repo.nii.ac.jp:00049039","sets":["3:2658:5762"]},"author_link":["204165"],"item_10_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2017","bibliographicIssueDateType":"Issued"}}]},"item_10_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"科学研究費助成事業 研究成果報告書:若手研究(B)2014-2016課題番号 : 26730026","subitem_description_language":"ja","subitem_description_type":"Other"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"金澤, 健治","creatorNameLang":"ja"},{"creatorName":"カナザワ, ケンジ","creatorNameLang":"ja-Kana"},{"creatorName":"Kanazawa, Kenji","creatorNameLang":"en"}],"nameIdentifiers":[{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2019-02-12"}],"displaytype":"detail","filename":"26730026seika.pdf","filesize":[{"value":"92.1 kB"}],"format":"application/pdf","mimetype":"application/pdf","url":{"objectType":"abstract","url":"https://tsukuba.repo.nii.ac.jp/record/49039/files/26730026seika.pdf"},"version_id":"95996ac3-ff07-4c12-a19f-34eeb4c9bf6d"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"research report","resourceuri":"http://purl.org/coar/resource_type/c_18ws"}]},"item_title":"マルチFPGAシステムにおける任意のデータアクセス幅のキャッシュ機構の実現","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチFPGAシステムにおける任意のデータアクセス幅のキャッシュ機構の実現","subitem_title_language":"ja"},{"subitem_title":"Arbitrary data-width cache memory architecture in multi-FPGA systems","subitem_title_language":"en"}]},"item_type_id":"10","owner":"1","path":["5762"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2019-02-12"},"publish_date":"2019-02-12","publish_status":"0","recid":"49039","relation_version_is_last":true,"title":["マルチFPGAシステムにおける任意のデータアクセス幅のキャッシュ機構の実現"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-03-29T23:47:01.211872+00:00"}