{"created":"2021-03-01T07:16:12.759471+00:00","id":37130,"links":{},"metadata":{"_buckets":{"deposit":"1fd98ba0-e9b8-4d7d-a7ed-efd719540325"},"_deposit":{"id":"37130","owners":[],"pid":{"revision_id":0,"type":"depid","value":"37130"},"status":"published"},"_oai":{"id":"oai:tsukuba.repo.nii.ac.jp:00037130","sets":["152:4929","3:62:5617:1403"]},"item_5_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2010-11-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicPageEnd":"2367","bibliographicPageStart":"2354","bibliographicVolumeNumber":"93","bibliographic_titles":[{"bibliographic_title":"電子情報通信学会論文誌. D, 情報・システム"},{"bibliographic_title":"The IEICE transactions on information and systems (Japanese edetion)","bibliographic_titleLang":"en"}]}]},"item_5_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"再構成可能集積回路と進化計算を用いて構成される進化型ハードウェアに動的部分再構成の機能を適用する.これにより,現実のパターン認識問題で環境の変化等により認識対象のデータに変化が生じた場合でも,即座に動的部分再構成を行い,環境の変化に適応することで常に高い認識精度を保つことができるシステムを提案する.また,パターン認識進化型ハードウェアの高速・高認識精度という特徴を損なうことなく,動的部分再構成を適用することにより,再構成中もパターン認識動作を止めることがない,ノンストップシステムを構築する.FPGA(Field Programmable Gate Array)を用いて提案手法に基づくシステムの実装をソナースペクトル認識を題材に行い,本研究の有効性を示す.提案手法は,従来のシステムよりも30倍以上高速なリコンフィギュレーションサイクルを実現し,現実のパターン認識問題にも十分対応できることを示す.","subitem_description_type":"Abstract"}]},"item_5_publisher_27":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"一般社団法人電子情報通信学会"}]},"item_5_publisher_28":{"attribute_name":"出版者別名","attribute_value_mlt":[{"subitem_publisher":"The Institute of Electronics, Information and Communication Engineers"}]},"item_5_relation_37":{"attribute_name":"関係URI","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"http://www.ieice.org/jpn/trans_online/index.html"}]}]},"item_5_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"一般社団法人電子情報通信学会"},{"subitem_rights":"本文データは学協会の許諾に基づきCiNiiから複製したものである"},{"subitem_rights":"http://ci.nii.ac.jp/naid/110007880359"}]},"item_5_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_5_source_id_7":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"18804535","subitem_source_identifier_type":"ISSN"}]},"item_5_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12099634","subitem_source_identifier_type":"NCID"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川合, 浩之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山口, 佳樹"},{"creatorName":"ヤマグチ, ヨシキ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"安永, 守利"},{"creatorName":"ヤスナガ, モリトシ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-02-18"}],"displaytype":"detail","filename":"110007880359.pdf","filesize":[{"value":"1.6 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"110007880359","url":"https://tsukuba.repo.nii.ac.jp/record/37130/files/110007880359.pdf"},"version_id":"14836cd1-119a-4450-a910-0b683401b451"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"動的部分再構成","subitem_subject_scheme":"Other"},{"subitem_subject":"パターン認識","subitem_subject_scheme":"Other"},{"subitem_subject":"進化型ハードウェア","subitem_subject_scheme":"Other"},{"subitem_subject":"遺伝的アルゴリズム","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア(計算機システム)","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア(計算機システム)"},{"subitem_title":"Development of High-Speed Evolvable Pattern Recognition Hardware Using Dynamic and Partial Reconfiguration","subitem_title_language":"en"}]},"item_type_id":"5","owner":"1","path":["4929","1403"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-02-18"},"publish_date":"2016-02-18","publish_status":"0","recid":"37130","relation_version_is_last":true,"title":["FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア(計算機システム)"],"weko_creator_id":"1","weko_shared_id":21},"updated":"2022-04-27T09:06:25.012932+00:00"}