2024-03-29T16:02:05Z
https://tsukuba.repo.nii.ac.jp/oai
oai:tsukuba.repo.nii.ac.jp:00042499
2024-02-06T00:48:59Z
152:1233
152:6075
3:62:5591:402
An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA
金澤, 健治
カナザワ, ケンジ
Kanazawa, Kenji
丸山, 勉
マルヤマ, ツトム
MARUYAMA, Tsutomu
open access
© 2017 The Institute of Electronics, Information and Communication Engineers
電子情報通信学会
Institute of Electronics, Information and Communication Engineers
2017-08
eng
journal article
VoR
http://hdl.handle.net/2241/00147401
https://tsukuba.repo.nii.ac.jp/records/42499
https://doi.org/10.1587/transinf.2016EDP7487
0916-8532
AA10826272
IEICE Transactions on Information and Systems
E100.D
8
1807
1818
https://tsukuba.repo.nii.ac.jp/record/42499/files/IEICETIS_E100D-8.pdf
application/pdf
1.0 MB
2017-09-06