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Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA
http://hdl.handle.net/2241/121196
http://hdl.handle.net/2241/121196b25ea9d9-98e2-40e5-90b0-09900e5d330b
名前 / ファイル | ライセンス | アクション |
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IEEETCS_61-2.pdf (1.8 MB)
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Item type | Journal Article(1) | |||||
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公開日 | 2014-04-04 | |||||
タイトル | ||||||
タイトル | Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源 | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
著者 |
At, Nuray
× At, Nuray× Beuchat, Jean-Luc× Okamoto, Eiji× San, Ismail× Yamazaki, Teppei |
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著者別名 |
岡本, 栄司
× 岡本, 栄司 |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms considered in this work to deeply pipeline our Arithmetic and Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count. | |||||
書誌情報 |
IEEE transactions on circuits and systems. I, Regular papers 巻 61, 号 2, p. 485-498, 発行日 2014-02 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 1549-8328 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11893184 | |||||
DOI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/TCSI.2013.2278385 | |||||
権利 | ||||||
権利情報 | © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
著者版フラグ | ||||||
値 | author | |||||
出版者 | ||||||
出版者 | IEEE Circuits and Systems Society | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2241/121196 | |||||
識別子タイプ | HDL | |||||
部分である | ||||||
関連タイプ | isPartOf | |||||
識別子タイプ | URI | |||||
関連識別子 | https://eprint.iacr.org/eprint-bin/print.pl |